1 Field of the Invention
The present invention relates to a power MOS gate type semiconductor device and a manufacturing method thereof, and more particularly, to a lateral MOS gate type semiconductor device including a Zener diode, and a manufacturing method thereof.
2. Description of the Related Art
Recently, power integrated circuit techniques for integrating a power semiconductor device having a high voltage and a large current and a driving circuit therefor into one chip have been rapidly developed. Lateral power semiconductor devices are generally used as power semiconductor devices which are incorporated into power integrated circuits. However, in lateral power semiconductor devices, current is horizontally conducted, and thus only a small amount of current can be conducted per unit area. Also, in the case of MOS gate type semiconductor devices, most of the current flows along the surface of the device, so that a small safe operating area is provided and ensuring reliability is not easy. Furthermore, when the lateral power semiconductor devices are connected to an inductive load, they cannot endure high avalanche energies.
FIG. 1 is a cross-sectional view showing the flow of drain current (indicated by the arrow) within a conventional lateral MOS gate type semiconductor device connected to an inductive load.
Referring to FIG. 1, an n-type low-concentration drift layer 2 is formed on an n-type high-concentration semiconductor substrate 1. The drift layer 2 can be formed by growing an n-type epitaxial layer on the semiconductor substrate 1. A p-type well region 3 is formed in a predetermined area below the upper surface of the drift layer 2. An n-type high-concentration source region 4 is formed within the p-type well region 3. An n-type high-concentration drain region 5 is formed below the surface of the n-type drift layer 2, being spaced a predetermined distance apart from the p-type well region 3. A gate electrode 7 is formed over a channel forming area of the p-type well region 3, having a gate oxide layer 6 interposed between the gate electrode 7 and the p-type well region. A source electrode 8 is formed such that it is electrically connected to the source region 4, and a drain electrode 9 is formed such that it is electrically connected to the drain region 5.
When the lateral MOS gate-type semiconductor device is connected to an inductive load and turned on, a considerable amount of energy is stored in the inductor of the inductive load, and must be discharged through the drain and source electrodes when the device is turned off. During this period, a high reverse voltage is applied between the drain and source electrodes, and thus the state of the junction portion between the p-type well region 3 and the n-type drift region 2 abruptly changes into an avalanche state. Then, a current from the inductor goes through a resistor (Rb) under the n-type high-concentration source region 4 via a parasitic pn diode formed by the junction portion between the p-type well region 3 and the n-type drift region 2, and flows into the source electrode 8 as indicated by an arrow in FIG. 1. Here, the drop in voltage across the resistor Rb forward-biases the junction portion between the p-type well region 3 and the n-type source region 4. When the voltage drop across the resistor Rb is greater than or equal to a predetermined value (i.e., 0.7V), carriers start being injected through the n-type high-concentration source region 4 as well as the p-type well region 3. That is, a parasitic npn bipolar junction transistor comprised of the n-type source region 4, the p-type well region 3, and the n-type drift region 2 starts being turned on. Therefore, the parasitic pn diode formed by the junction portion between the p-type well region 3 and the n-type drift region 2 can resist avalanche energies only until the parasitic npn bipolar junction transistor is turned on.
However, a general lateral MOS gate-type transistor includes a parasitic pn diode of a small capacity, and furthermore cannot resist high avalanche energies because it is easy to turn on the parasitic bipolar junction transistor, as described above. Hence, it is very important to avoid turn-on of the parasitic bipolar junction transistor so that the parasitic bipolar junction transistor can endure the high avalanche energies.
To do this, there has been proposed a method of reducing the value of the resistor Rb under the n-type high-concentration source region by increasing the concentration of the p-type well region, in the prior art. However, this method has problems in that the threshold voltage increases, the current conducting ability is degraded, and the step of forming a mask film must be added in the device manufacturing method. There is also a method in which the device can resist avalanche energies by virtue of a special diode installed at the exterior of the device. This method increases the cost, and becomes quite complicated in terms of system design.
To solve the above problems, it is an object of the present invention to provide a lateral MOS gate-type semiconductor device including a Zener diode, which can resist a large amount of avalanche energy without turning on a parasitic bipolar transistor.
It is another object of the present invention to provide a method of manufacturing the lateral MOS gate-type semiconductor device including a Zener diode.
Accordingly, to achieve the first object, a lateral MOS gate semiconductor device according to an embodiment of the present invention incudes a drift layer of a first conductivity type, formed on a semiconductor substrate, and a well region of a second conductivity type that is opposite to the first conductivity type, formed in a given area below the upper surface of the drift layer. A first high-concentration source region is formed in a given area in the well region, and a high-concentration drain region of a first conductivity type is separated from the well region by a predetermined distance in a predetermined area below the upper surface of the drift layer. A plurality of Zener diodes having a predetermined breakdown voltage are separated from the drift layer to act as a passage for moving carriers from the drain region to the source region. A gate electrode is formed on a predetermined channel forming area of the well region, having a gate insulative film formed between the gate electrode and the predetermined channel forming area. A source electrode is formed so as to be electrically connected to the source region. A drain electrode is formed so as to be electrically connected to the drain region.
In the present invention, the semiconductor substrate is of a first conductivity type high concentration or a second conductivity type high-concentration. When the semiconductor substrate is of the first conductivity type, the lateral MOS gate-type semiconductor device further incudes an insulative film interposed between the semiconductor substrate and the drift layer.
It is preferable that first conductive regions and second conductive regions constituting the Zener diodes are connected to each other in series, perpendicularly to the direction of current flow in the drift layer. Here, the first and second conductive regions alternate within the polycrystalline silicon film, and the first conductive regions are positioned at both ends of the polycrystalline silicon film. In particular, it is preferable that one first conductive region of the two positioned at both ends of the polycrystalline silicon film is connected directly to the drain region, and the other first conductive region is connected to the source region. The first conductive region connected to the source region can be connected directly to the source region, or connected to the source region via the gate electrode.
In some circumstances, the first conductive regions and second conductive regions constituting the Zener diodes can be connected to each other in series such that they are parallel to the direction of current flow in the drift layer. In this case, the first and second conductive regions alternate within the polycrystalline silicon film, and the first conductive region and the second conductive region are positioned respectively at both ends of the polycrystalline silicon film. The first conductive region positioned at one end of the polycrystalline silicon film is connected directly to the drain region, and the second conductive region positioned at the other end of the polycrystalline silicon film is connected directly to the gate electrode. Here, it is preferable that the gate electrode is of a first conductivity type. Also, it is preferable that a diode for acting as a passage for the flow of current from the Zener diodes into the source region is further formed between the gate electrode and the source region.
FIG. 5 is a perspective view of a MOS gate-type semiconductor device including a Zener diode, according to a second embodiment of the present invention. In the first embodiment described referring to FIG. 2, no problems occur when the first embodiment is used as an independent device. However, when several devices are formed together within the same substrate as in a BiCDMOS device, problems occur. For example, when the n-type drift layer 110 of FIG. 2 is also used as the well region of another device, e.g., a CMOS transistor, other devices can be damaged by an excessive drain voltage. In order to prevent this problem, a high-concentration isolation region must be formed between adjacent devices. In the second embodiment, to solve the above problem, a p-type substrate is used as a semiconductor substrate, and an n-type well region is formed in the drain region, thereby preventing an influence on other devices formed on the same substrate. This is the difference from the first embodiment.
To achieve the first object, a lateral MOS gate semiconductor device according to another embodiment of the present invention includes a well region of the first conductivity type and a well region of a second conductivity type formed in areas below the upper surface of a semiconductor substrate of a first conductivity type such that they are a predetermined distance apart from each other. A high-concentration source region of the second conductivity type is formed in a given area in the well region of the first conductivity type, and a high-concentration drain region of the second conductivity type is formed in a predetermined area in the well region of the second conductivity type. A plurality of Zener diodes having a predetermined breakdown voltage are separated from the semiconductor substrate to act as a passage for moving carriers from the drain region to the source region. A gate electrode is formed on a channel forming area of the well region of the second conductivity type, having a gate insulative film interposed between the gate electrode and the channel forming area. A source electrode is formed so as to be electrically connected to the source region. A drain electrode is formed so as to be electrically connected to the drain region.
To achieve the second object, in a method of manufacturing a lateral MOS gate semiconductor device according to an embodiment of the present invention, an oxide film is formed on a semiconductor substrate, and a field oxide film for defining active regions is formed by growing only part of the oxide film. A polycrystalline silicon film is formed on the oxide film and the field oxide film, and then patterned, thus forming a first polycrystalline silicon film for gate electrodes and a second polycrystalline silicon film for Zener diodes. A first mask film pattern for forming a well region and the first conductive regions of the second polycrystalline silicon film, is formed, and impurity ions of a first conductivity type are implanted using the first mask film pattern as an ion implantation mask. A second mask film pattern for forming a source region, a drain region, and the regions of the second conductivity type of the second polycrystalline silicon film, is formed, and impurity ions of the second conductivity type are implanted using the second mask film pattern as an ion implantation mask. Then, the impurity ions of the first and second conductivity types are drive-in implanted.
Here, it is preferable that the step of electrically connecting the two regions of the first conductivity types formed at both ends of the second polycrystalline silicon film, to the drain region and the source region, respectively, is further included.
To achieve the second object, in a method of manufacturing a lateral MOS gate semiconductor device according to another embodiment of the present invention, an oxide film is formed on a semiconductor substrate, and a field oxide film for defining active regions is formed by growing only part of the oxide film. A polycrystalline silicon film is formed on the oxide film and the field oxide film. A first mask film pattern for forming a well region, a gate electrode, and the first conductivity type regions of Zener diodes on the polycrystalline silicon film, is formed on the polycrystalline silicon film. Impurity ions of the first conductivity type are implanted using the first mask film pattern as an ion implantation mask. A second mask film pattern for forming a source region, a drain region, and the second conductivity type regions of the Zener diodes, is formed on the polycrystalline silicon film. Impurity ions of the second conductivity type are implanted using the second mask film pattern as an ion implantation mask. The first and second impurity ions are drive-in diffused.
Here, it is preferable that the method further includes the steps of: electrically connecting a first conductivity type region which is the closest to the drain region, among the first conductivity type regions of the Zener diodes, to the drain region; and electrically connecting the gate electrode to the source region.
In the MOS gate-type semiconductor device including a Zener diode according to the present invention, Zener diodes, which are separated from a parasitic diode within the device and and have a relatively small breakdown voltage, are each connected to the drain and source regions. Accordingly, even when a high reverse voltage is applied, the Zener diode breaks down before the parasitic diode breaks down. Thus, even when a high reverse voltage is applied, a parasitic bipolar junction transistor is not turned on. Therefore, the device can endure high avalanche energies due to an inductive load when it is turned off, so that the ruggedness and the stability of the device are improved. Also, according to a manufacturing method thereof, the Zener diode can be incorporated into the MOS gate-type semiconductor device without forming an additional mask layer.